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Texas Instruments /MSP432P4011 /DWT /DWT_LSUCNT

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Interpret as DWT_LSUCNT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LSUCNT

Description

DWT LSU Count Register

Fields

LSUCNT

LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling.

Links

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Register License

Copyright © 2012-2018 Texas Instruments Incorporated - http://www.ti.com/

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Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data